Breaking The Bottleneck In Semiconductor Fabrication

FAYETTEVILLE, Ark. - Integrated circuits (IC) run our lives. They control the alarm clock that wakes us and the appliance that automatically has a pot of coffee ready when we walk into the kitchen, the system that monitors every detail of our car’s performance and the system that controls traffic signals. They are essential to our computers, our telephones, and our way of life. But they are not easy to make.

University of Arkansas researcher Scott Mason is working with a consortium comprising the University of Arkansas, Arizona State University, and three German institutions (University of Wuerzburg, Technical University of Ilmenau, and the Fraunhofer Institute) to improve this manufacturing process, which will increase productivity and reduce costs. He presented the results of his research last week at the International Conference on Flexible Automation and Intelligent Manufacturing in Dresden, Germany.

Because they are very small, ICs are produced in quantity on a large silicon wafer substrate, then sawed into individual microchips. Currently, the standard wafer is 200 mm (8 inches) in diameter.

"If we can improve efficiency and throughput by only one wafer a day, it will have a significant effect," Mason explained. "A typical 200 mm wafer fabrication facility represents a $2 billion investment and 300 mm fabs come with a $3.5 billion price tag. Each wafer can be worth over $100,000 and they are produced in lots of 25. At any given time, the inventory in a fab could exceed $0.5 billion."

The semiconductor industry is currently transitioning to an increased wafer size of 300 mm (12 in.), making each wafer even more valuable. While this can double the number of ICs on a wafer, it also complicates a process that was already highly complex.

Dozens of process flows are involved in the fabrication of an IC. Each process flow contains 400-600 steps and uses more than 100 machines, which range in cost from $50,000 to more than $10 million per tool. At those prices, it is not practical to buy excess tools, so the equipment must be shared at many stages in the production process.

The process is further complicated by random equipment failures, scheduled tool maintenance, scarce auxiliary resources and the duration and nature of the various operations. Some operations may require only 15 minutes, while others take up to 12 hours. In addition, some machines, like ion implanters, must be set up in the proper sequence, and setup time alone can cause significant delays.

Although the process is immensely more expensive and complicated, Mason likens it to baking a cake. A typical cake will have a variety of ingredients that must be combined in a specific order and quantity if the cake is to be a success. The baker will use several different tools--a mixer, a whisk, bowls, a sifter, pans, chopping tools, spoons, spatulas, ovens, etc. But the baking process also must be done in the correct order.

"In this analogy, a process step might be where you measure and sift together the dry ingredients and put them in a bowl," explained Mason. "Another process step would be combining some ingredients with the mixer, and then adding the dry ingredients. The mixer might also be used by another step, beating the egg whites, for example."

Some processes, such as sifting, might take only a minute, while others, like mixing, might tike 5 minutes. And, like semiconductor wafer fabrication, it is important that each process be done in the correct order to produce a quality product.

Currently wafer fab managers typically develop a production schedule for each day, but bottlenecks, breakdowns and other factors can severely distort the schedule. Recognizing and adjusting for these problems is complex and difficult.

Mason and his research team are developing scheduling methodologies for wafer fabrication that will incorporate methods to recognize and overcome these problems. The resulting approach will work with the existing manufacturing execution software at companies like Intel and Texas Instruments to improve workflow.

"Our goal is to make something that is actually used in industry, not to solve an academic problem," said Mason. "Our results should make scheduling a wafer fab on a shift-by-shift basis - or even more frequently - a real possibility."



Scott Mason, assistant professor of industrial engineering, (479) 575-5521;

Carolyne Garcia, science and research communication officer, (479) 575-5555;



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