AUTOMATIC MODELS SPEED UP CREATION OF SYSTEM-ON-A-CHIP

FAYETTEVILLE, Ark. - System-on-a-chip (SOC) is the hottest new approach to making electronics smaller, faster and cheaper, but these complex systems require tedious, slow and expensive testing before they can be built. University of Arkansas researcher Alan Mantooth is working on a computer model that will make producing SOCs feasible for consumer products.

"SOC is where chip technology is headed," said Mantooth. "It is essential for making electronic devices smaller. With SOC technology, the next generation of cell phones may be the size of a watch or an earpiece."

Mantooth leads a team of researchers that received a grant from the Defense Advanced Research Projects Agency (DARPA) that will total more than $1.3 million. The grant, awarded through the Space Warfare Center, will be announced in an official ceremony on August 29 in Malibu, Calif.

"The SOC integrates all of the functions of a computer and more onto a single silicon chip," explained Mantooth. " That means combining processors, memory devices, communications peripherals and analog devices on one chip. SOC is a simple idea, but complex to design and produce."

One of the biggest challenges in SOC design and production is testing. Physical testing is prohibitively expensive, as is building multiple physical prototypes, so designers must rely on computer models - virtual prototypes - and simulations to test their designs before the SOC is produced. Test engineers also use these models to develop automated tests to physically test the chips once they are produced.

"Chip designers must maintain the accuracy of certain performance characteristics while improving productivity. This means that they must verify their work many times during SOC design," said Mantooth. "To overcome these challenges, we will build a behavioral modeling tool that will create models for SOC design at the system level. Currently no behavioral models exist for chip design."

Behavioral models are used in two phases of the design process. At the concept level, the models are used in a top-down approach that determines if a concept is feasible and at the design stage it is a bottom-up look at how each component of the system works together throughout the system.

Modeling each individual component of the system is both expensive and time-consuming, In addition, when combined the components may behave differently than they do as individual parts. Mantooth’s team is working to automate the process of creating the behavioral models for the components of the system, including the interactions with neighboring components.

"Automation is the only way that a system this highly complex can be modeld and simulated in a timely manner before chip fabrication," Mantooth explained. "The trick is in teaching the computer to do what the human mind can do - to extract relevant data. Building intelligence into the computer will allow it to make interpretations, enabling it to generate behavioral models automatically."

In addition to U of A faculty, Mantooth’s team includes Richard Shi, professor of electrical engineering at the University of Washington. They will develop the algorithms for an automated design tool that will allow SOC designers to simulate the entire system at once.

"We are very proud of the success of our proposal," said Mantooth. "This was an open solicitation, so we were competing against institutions like MIT and the University of California, as well as industry and government laboratories around the world. This is a great opportunity and we are looking forward to the challenges."