CSCE Assistant Professor Yarui Peng Receives the Prestigious NSF CAREER Award to Study Design Automation Tools for Heterogeneous Multi-Chiplet Systems
Yarui Peng, assistant professor of computer science and computer engineering, has received the NSF Faculty Early Career Development Award in 2021, known as a CAREER award. NSF describes the CAREER Award as its most prestigious award in support of early-career faculty who have the potential to serve as academic role models in research and education and to lead advances in the mission of their department and organization.
The NSF CAREER award, titled "Chiplet-Package Co-Optimizations for 2.5D Heterogeneous SoCs with Low-Overhead IOs," is funded by Software and Hardware Foundations (SHF) of Computing and Communication Foundations (CCF) Division. It provides $500,000 over five years to support Peng's research and education programs to develop computer-aided design tools, design IC chips and study methodologies to combine heterogeneous chiplets within a single package, maximizing system performance, density and power savings with minimum design overhead.
Peng joined the department since 2017 and leads the Energy-Efficient Electronics and Design Automation (E3DA) Lab. His research focused on computer-aided design tools for advanced multi-chip IC design and packaging solutions. He is also working with the U of A power group and the NSF POETS engineering research center on design automation tools for power electronics. His goal is to enable seamless heterogeneous integration between not only just digital Si chips, but also analog, MEMS and SiC/GaN power devices. Imagine a laptop without the bulky and heavy power adapter any more. His secret recipe is designing hardware using software tools to avoid repetitive or redundant procedures and optimize heterogeneous design solutions, combining intelligence from both engineers and computers.
With Moore's Law reaching physical limits, 2.5D/3D designs are becoming increasingly popular as scalable solutions to push computational performance. AMD's Zen, Intel's Lakefield and Nvidia's A100 are all great examples. However, the traditional design flow separates engineers and tools into two distinct domains and isolates IC and packaging societies, resulting in inevitable performance and energy gaps. Peng proposes to combine IC and package designs through a seamless open-sourced framework for heterogeneous development. Heterogeneous integration maximizes the flexibility by reusing chiplets from different vendors and foundries so each IP block can be implemented using the optimum technology node.
Peng and his team will develop new tools called "IO Synthesis," create libraries of IO cells, and place them among logic gates at perfect locations. It will be followed by careful analysis and parasitic extraction, which allow CAD tools to smartly pick the exact sizing of logic gates and IO cells and minimize the overhead. All components forming the system will be considered in a holistic way to provide the highest accuracy and optimization levels possible. Chips will be taped out to validate their design flow. Further, they will explore the potential of heterogeneous integration of Si chips with SiC power electronics through another tool called PowerSynth, co-developed with the U of A Power Group. Overall, their target is to minimize inter-chiplet overhead, reduce design costs, explore the full potential of 2.5D/3D systems and demonstrate the highest performance, density and efficiency with heterogeneous multi-chiplet integration.
In addition, Peng will also extend his research with collaboration and education to train the next generation of engineers. Students will have a chance to work with software and hardware companies in Silicon Valley and rising industries in power electronics and electrified vehicles. He is also creating new CSCE courses, training young researchers and expanding diversity through Honors' Research and NSF PATH programs. He has been and will continue to work with the U of A Power Group on REU and RET programs, to provide lab tours, training sessions and outreach to local high school students and teachers. The industry and community will benefit from well-trained interns and students, open-source CAD tools and 2.5D heterogeneous designs through this CAREER award.
Details of Peng's Research and Education programs can be found on the E3DA lab website: https://e3da.csce.uark.edu/.
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